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Enablement_Design_Aids & Automation Engineering professional

Experis

This is a Full-time position in Albany, NY posted January 10, 2022.

Job Title: Design Aids & Automation Engineer
Location: Essex Junction, VT OR consider remote individuals and Albany, NY

Additional Details:
* looking for candidates with 2+ years of experience

Job Duties:
1 – Develop test structure layout using design automation per specified requirements, using industry standard (EDA) tools including Cadence Virtuoso Design Environment and SKILL code.
2 – Develop layout regression testcases for Design Rule Checking (DRC) decks based on specified Design Rule Manual (DRM) requirements, using industry standard (EDA) tools including Synopsys IC Validator.
3- Develop manual layout cells per specified requirements, using industry standard (EDA) tools including Cadence Virtuoso Design Environment.
4 – Develop regression testcases for Layout Versus Schematic (LVS) decks based on specified Design Rule Manual (DRM) and device list requirements, using industry standard (EDA) tools including Synopsys IC Validator.
5 – Interpret Design Rules. Work closely with Design Rule engineers and DRC / LVS development engineers to validate DRC / LVS decks.
6 – Work on automated regression testcase projects to increase efficiency and coverage of regressions, using Python to create testcases.
7 – Debug and solve problems in a team environment.

Basic Skills, clearances and other elements required, in order of importance, and number of years’ experience, where applicable, in each skill:
1) Experience with running DRC / LVS decks in either Mentor Graphics Calibre or Synopsys ICV language, and debugging layouts, at least 2 years.
2) Experience using the Cadence Virtuoso layout design tool or other EDA layout design tool, at least 2 years.
3) Strong understanding of physical layout, technology groundrules, and semiconductor processing.
4) Experience with Cadence Skill programming language, at least 2 years.
5) Experience in coding for Java, C++, and Python for automation.
6) Ability to debug errors and solve problems.
7) Ability to work in a team environment.
8) Fluent English (both verbal and written) and strong communication skills.

Other Skills Desired, Years in each skill, where applicable:
1) Preferred: Experience with advanced sub-micron semiconductor technology nodes.
2) Preferred: Experienced user of Synopsys ICV DRC / LVS checking tools.
3) Preferred: Experience with Cadence SKILL programming language for pcell development & design automation